The present invention relates broadly to the field of digital computers and specifically to microprogram controlled computers having a multi-level priority interrupt of the controller.
Digital computer systems typically have a computer program which specifies the particular operation which can occur at one particular moment. In time shared systems, the system has the appearance of running more than one program at the same time. In either environment, however, the computer system must be able to handle interrupts to the operation of the program. These interrupts are most frequently caused by input/output devices requesting some form of service from the processor. The interrupt causes the processor to stop what it is doing and take up the task requested by the interrupting device.
Processing of any given interrupt does take some time. In prior art computers capable of handling a single interrupt at a time, higher priority interrupt conditions may occur during the processing of a lower priority interrupt. Since but one interrupt could be processed at a time, the higher priority interrupt had to wait until the lower priority interrupt was handled. This result is not necessarily acceptable in systems having very high speed input/output devices which need service.
One possible solution to this problem is to design special purpose hardware to handle high speed interrupts directly and not utilize the micro-program at all. In order to do this, however, a considerable amount of hardware is necessary. This is undesirable in machines designed to be small and inexpensive as the increased hardware requires more physical space and increases the cost.
It is accordingly a primary objective of the present invention to provide a multi-level priority micro-interrupt controller for a digital computer system.
It is another objective of the present invention to provide a multi-level priority micro-interrupt controller which is physically small so that the computer itself can be made small compared to prior systems of comparable processing capability.
It is yet another objective of the present invention to provide a multi-level priority micro-interrupt controller which is implemented with few circuits so that cost of these circuits is small compared to the total cost of the system.